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C-element
The Muller C-element (C-gate or sometimes, Hysteresis flip-flop) is a commonly used asynchronous logic component originally devised by David E. Muller.〔(D. E. Muller, W. S. Bartky, "A theory of asynchronous circuits I," Report no. 75, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1956. )〕〔(D. E. Muller, W. S. Bartky, "A theory of asynchronous circuits II," Report no. 78, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1957. )〕〔(W. S. Bartky, "A theory of asynchronous circuits III," Report no. 96, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1960. )〕 The output of the C-element applies logical operations on the inputs and has state or logical hysteresis. When all the inputs go high, the output switches to high. It stays in this state until all the inputs go low, at which time the output switches to low.〔(W. Fleischhammer, "Improvements in or relating to asynchronous bistable trigger circuits," UK patent specification GB1199698, Jul. 22, 1970 )〕〔(M. Kuwako, T. Nanya, "Timing-reliability evaluation of asynchronous circuits based on different delay models," IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC) 1994, pp.22-31. )〕〔(J. Cortadella, M. Kishinevsky, Tutorial: Synthesis of control circuits from STG specifications. Summer school, Lyngby, 1997 )〕 This behavior can be extended to the asymmetric C-element where some inputs only affect the operation in one of the transitions (positive or negative).
== Truth table and delay assumptions ==
For two input signals the C-element is defined by the equation , which corresponds to the following truth table.
This table can be turned into a circuit using the Karnaugh map. However, the obtained implementation is naïve, since nothing is said about delay assumptions. To understand under what conditions the obtained circuit is workable, it is necessary to do additional analysis, which reveals that
* delay1 is a propagation delay from node 1 via environment to node 3
* delay2 is a propagation delay from node 1 via internal feedback to node 3
* delay1 must be greater than delay2
Thus, the naïve implementation is correct only for slow environment.
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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